1. Field of the Invention
The present invention relates to an unsigned integer comparator and, more particularly, to an unsigned integer comparator useful in high speed data circuits.
2. Description of the Prior Art
In address arithmetic units, as well as address watchpoint units, it is important to know if the current address is "equal to" (E) or "greater than/equal to" (GE) to a specified address, where address values are always unsigned integers. In most data circuit arrangements, it is required that such comparison be completed in one clock cycle (or less). One prior art approach to performing this comparison, included in current digital signal processor designs, utilizes the carry chain of a fast n bit adder, where n is the word length of the address. The delay involved in this comparison process is determined by the n-bit carry propagation delay. Further, extra time is required to select between E and GE, as well as to pass the selected E or GE indication to the output decision step. An approach to reducing the delay associated with conventional comparators is to increase the processing speed of the "fast" n bit adder. However, processing technology limitations are foreseen to limit the additional speed that may be gained by this approach.
Therefore, a need remains in the art for an unsigned integer comparator that is capable of processing unsigned integers at the speeds required for next generation circuit designs.